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2 | (24) |
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Numerical Representations |
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4 | (1) |
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Digital and Analog Systems |
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5 | (4) |
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9 | (4) |
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Representing Binary Quantities |
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13 | (2) |
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Digital Circuits/Logic Circuits |
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15 | (1) |
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Parallel and Serial Transmission |
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16 | (2) |
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18 | (1) |
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18 | (6) |
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24 | (32) |
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Binary-to-Decimal Conversions |
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26 | (1) |
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Decimal-to-Binary Conversions |
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27 | (3) |
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30 | (3) |
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Hexadecimal Number System |
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33 | (5) |
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38 | (2) |
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40 | (1) |
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The Byte, Nibble, and Word |
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41 | (1) |
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42 | (3) |
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Parity Method for Error Detection |
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45 | (3) |
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48 | (8) |
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Describing Logic Circuits |
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56 | (64) |
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Boolean Constants and Variables |
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58 | (1) |
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59 | (1) |
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Or Operation with Or Gates |
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60 | (4) |
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And Operation with And Gates |
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64 | (3) |
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67 | (1) |
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Describing Logic Circuits Algebraically |
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68 | (2) |
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Evaluating Logic-Circuit Outputs |
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70 | (2) |
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Implementing Circuits from Boolean Expressions |
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72 | (2) |
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74 | (3) |
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77 | (4) |
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81 | (4) |
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Universality of Nand Gates and Nor Gates |
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85 | (4) |
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Alternate Logic-Gate Representations |
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89 | (3) |
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Which Gate Representation to Use |
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92 | (5) |
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IEEE/ANSI Standard Logic Symbols |
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97 | (2) |
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Summary of Methods to Describe Logic Circuits |
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99 | (2) |
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Description Languages Versus Programming Languages |
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101 | (2) |
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Implementing Logic Circuits with PLDs |
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103 | (2) |
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105 | (3) |
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108 | (12) |
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Combinational Logic Circuits |
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120 | (92) |
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122 | (1) |
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Simplifying Logic Circuits |
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123 | (1) |
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124 | (5) |
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Designing Combinational Logic Circuits |
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129 | (7) |
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136 | (11) |
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Exclusive-Or and Exclusive-Nor Circuits |
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147 | (6) |
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Parity Generator and Checker |
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153 | (2) |
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155 | (2) |
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Basic Characteristics of Digital ICs |
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157 | (7) |
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Troubleshooting Digital Systems |
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164 | (2) |
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Internal Digital IC Faults |
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166 | (4) |
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170 | (2) |
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Troubleshooting Case Study |
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172 | (2) |
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Programmable Logic Devices |
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174 | (7) |
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181 | (4) |
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185 | (3) |
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Decision Control Structures in HDL |
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188 | (24) |
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Flip-Flops and Related Devices |
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212 | (92) |
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215 | (5) |
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220 | (3) |
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Troubleshooting Case Study |
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223 | (2) |
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Clock Signals and Clocked Flip-Flops |
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225 | (2) |
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227 | (4) |
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231 | (2) |
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233 | (2) |
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D Latch (Transparent Latch) |
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235 | (2) |
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237 | (3) |
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240 | (2) |
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Flip-Flop Timing Considerations |
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242 | (3) |
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Potential Timing Problem in FF Circuits |
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245 | (2) |
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247 | (1) |
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247 | (1) |
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Flip-Flop Synchronization |
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248 | (1) |
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Detecting an Input Sequence |
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249 | (1) |
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Data Storage and Transfer |
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250 | (2) |
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Serial Data Transfer: Shift Registers |
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252 | (4) |
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Frequency Division and Counting |
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256 | (4) |
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Microcomputer Application |
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260 | (1) |
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261 | (2) |
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One-Shot (Monostable Multivibrator) |
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263 | (3) |
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Analyzing Sequential Circuits |
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266 | (2) |
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268 | (2) |
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Troubleshooting Flip-Flop Circuits |
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270 | (5) |
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Sequential Circuits Using HDL |
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275 | (3) |
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278 | (7) |
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HDL Circuits with Multiple Components |
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285 | (19) |
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Digital Arithmetic: Operations and Circuits |
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304 | (74) |
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306 | (1) |
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Representing Signed Numbers |
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307 | (7) |
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Addition in the 2's-Complement System |
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314 | (1) |
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Subtraction in the 2's-Complement System |
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315 | (2) |
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Multiplication of Binary Numbers |
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317 | (1) |
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318 | (1) |
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319 | (2) |
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321 | (3) |
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324 | (1) |
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325 | (2) |
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327 | (3) |
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Complete Parallel Adder with Registers |
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330 | (2) |
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332 | (1) |
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Integrated-Circuit Parallel Adder |
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333 | (2) |
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335 | (4) |
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339 | (3) |
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342 | (4) |
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346 | (1) |
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Troubleshooting Case Study |
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347 | (1) |
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Using TTL Library Functions with HDL |
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348 | (6) |
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Logical Operations on Bit Arrays |
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354 | (2) |
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356 | (3) |
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Expanding the Bit Capacity of a Circuit |
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359 | (19) |
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378 | (116) |
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Asynchronous (Ripple) Counters |
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380 | (3) |
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Counters with MOD Numbers < 2N |
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383 | (6) |
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389 | (5) |
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Asynchronous Down Counter |
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394 | (2) |
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Propagation Delay in Ripple Counters |
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396 | (2) |
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Synchronous (Parallel) Counters |
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398 | (3) |
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Synchronous Down and Up/Down Counters |
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401 | (1) |
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402 | (2) |
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404 | (6) |
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More on the IEEE/ANSI Dependency Notation |
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410 | (2) |
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412 | (3) |
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415 | (3) |
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418 | (1) |
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Synchronous Counter Design |
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419 | (8) |
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427 | (7) |
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Full-Featured Counters in HDL |
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434 | (4) |
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438 | (2) |
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440 | (5) |
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Integrated-Circuit Registers |
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445 | (1) |
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Parallel In/Parallel Out---The 74ALS174/74HC174 |
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445 | (2) |
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Serial In/Serial Out---The 4731B |
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447 | (1) |
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Parallel In/Serial Out---The 74ALS165/74HC165 |
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448 | (1) |
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Serial In/Parallel Out---The 74ALS164/74HC164 |
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449 | (2) |
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IEEE/ANSI Register Symbols |
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451 | (2) |
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453 | (4) |
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457 | (2) |
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459 | (6) |
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465 | (1) |
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466 | (28) |
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Integrated-Circuit Logic Families |
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494 | (88) |
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496 | (8) |
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504 | (5) |
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509 | (4) |
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TTL Series Characteristics |
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513 | (3) |
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516 | (5) |
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Other TTL Characteristics |
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521 | (4) |
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525 | (2) |
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527 | (1) |
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528 | (2) |
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CMOS Series Characteristics |
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530 | (7) |
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537 | (3) |
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Open-Collector/Open-Drain Outputs |
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540 | (5) |
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Tristate (Three-State) Logic Outputs |
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545 | (3) |
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High-Speed Bus Interface Logic |
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548 | (2) |
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The ECL Digital IC Family |
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550 | (3) |
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CMOS Transmission Gate (Bilateral Switch) |
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553 | (2) |
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555 | (1) |
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556 | (2) |
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558 | (2) |
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Analog Voltage Comparators |
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560 | (2) |
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562 | (20) |
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582 | (100) |
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583 | (8) |
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BCD-to-7-Segment Decoder/Drivers |
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591 | (2) |
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593 | (4) |
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597 | (5) |
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602 | (2) |
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Multiplexers (Data Selectors) |
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604 | (6) |
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610 | (5) |
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Demultiplexers (Data Distributors) |
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615 | (8) |
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623 | (4) |
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627 | (3) |
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630 | (4) |
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634 | (1) |
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The 74ALS173/HC173 Tristate Register |
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635 | (3) |
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638 | (6) |
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644 | (4) |
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The HDL 7-Segment Decoder/Driver |
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648 | (3) |
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651 | (3) |
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HDL Multiplexers and Demultiplexers |
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654 | (4) |
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HDL Magnitude Comparators |
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658 | (1) |
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659 | (23) |
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Digital System Projects Using HDL |
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682 | (42) |
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684 | (1) |
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Stepper Motor Driver Project |
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685 | (8) |
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693 | (6) |
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699 | (17) |
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Frequency Counter Project |
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716 | (8) |
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Interfacing with the Analog World |
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724 | (70) |
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Review of Digital Versus Analog |
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725 | (2) |
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Digital-to-Analog Conversion |
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727 | (9) |
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736 | (5) |
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741 | (2) |
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An Integrated-Circuit DAC |
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743 | (1) |
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744 | (1) |
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745 | (1) |
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Analog-to-Digital Conversion |
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746 | (2) |
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748 | (4) |
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752 | (4) |
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Successive-Approximation ADC |
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756 | (6) |
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762 | (2) |
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Other A/D Conversion Methods |
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764 | (4) |
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768 | (3) |
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771 | (1) |
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772 | (2) |
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Digital Storage Oscilloscope |
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774 | (1) |
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Digital Signal Processing (DSP) |
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775 | (19) |
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794 | (88) |
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797 | (3) |
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800 | (3) |
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803 | (2) |
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805 | (2) |
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807 | (2) |
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809 | (1) |
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810 | (9) |
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819 | (4) |
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823 | (4) |
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827 | (1) |
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827 | (3) |
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830 | (5) |
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835 | (1) |
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Dynamic RAM Structure and Operation |
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836 | (5) |
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841 | (2) |
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843 | (3) |
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846 | (2) |
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Expanding Word Size and Capacity |
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848 | (8) |
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856 | (3) |
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Troubleshooting RAM Systems |
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859 | (8) |
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867 | (15) |
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Programmable Logic Device Architectures |
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882 | (30) |
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Digital Systems Family Tree |
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884 | (5) |
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Fundamentals of PLD Circuitry |
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889 | (3) |
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892 | (4) |
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The GAL 16V8 (Generic Array Logic) |
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896 | (4) |
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900 | (4) |
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The Altera FLEX10K Family |
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904 | (8) |
Glossary |
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912 | (13) |
Answers to Selected Problems |
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925 | (18) |
Index of ICs |
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943 | (3) |
Index |
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946 | |