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2 | (22) |
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Numerical Representations |
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4 | (1) |
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Digital and Analog Systems |
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5 | (5) |
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10 | (3) |
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Representing Binary Quantities |
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13 | (2) |
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Digital Circuits/Logic Circuits |
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15 | (2) |
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Parallel and Serial Transmission |
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17 | (1) |
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18 | (1) |
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19 | (5) |
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24 | (30) |
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Binary-to-Decimal Conversions |
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26 | (1) |
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Decimal-to-Binary Conversions |
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26 | (3) |
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Hexadecimal Number System |
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29 | (4) |
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33 | (2) |
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35 | (2) |
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37 | (1) |
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The Byte, Nibble, and Word |
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37 | (2) |
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39 | (2) |
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Parity Method for Error Detection |
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41 | (3) |
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44 | (10) |
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Describing Logic Circuits |
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54 | (64) |
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Boolean Constants and Variables |
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57 | (1) |
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57 | (1) |
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OR Operation with OR Gates |
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58 | (4) |
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And Operation with And Gates |
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62 | (3) |
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65 | (1) |
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Describing Logic Circuits Algebraically |
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66 | (2) |
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Evaluating Logic-Circuit Outputs |
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68 | (3) |
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Implementing Circuits from Boolean Expressions |
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71 | (2) |
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73 | (3) |
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76 | (4) |
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80 | (3) |
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Universality of NAND Gates and NOR Gates |
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83 | (3) |
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Alternate Logic-Gate Representations |
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86 | (3) |
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Which Gate Representation to Use |
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89 | (6) |
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IEEE/ANSI Standard Logic Symbols |
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95 | (1) |
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Summary of Methods to Describe Logic Circuits |
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96 | (2) |
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Description Languages Versus Programming Languages |
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98 | (2) |
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Implementing Logic Circuits with PLDs |
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100 | (2) |
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102 | (3) |
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105 | (13) |
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Combinational Logic Circuits |
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118 | (90) |
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120 | (1) |
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Simplifying Logic Circuits |
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121 | (1) |
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121 | (6) |
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Designing Combinational Logic Circuits |
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127 | (6) |
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133 | (11) |
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Exclusive-OR and Exclusive-NOR Circuits |
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144 | (5) |
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Parity Generator and Checker |
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149 | (2) |
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151 | (2) |
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Basic Characteristics of Digital ICs |
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153 | (7) |
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Troubleshooting Digital Systems |
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160 | (2) |
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Internal Digital IC Faults |
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162 | (4) |
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166 | (2) |
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Troubleshooting Case Study |
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168 | (2) |
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Programmable Logic Devices |
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170 | (7) |
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177 | (4) |
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181 | (3) |
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Decision Control Structures in HDL |
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184 | (24) |
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Flip-Flops and Related Devices |
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208 | (88) |
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211 | (5) |
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216 | (3) |
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Troubleshooting Case Study |
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219 | (1) |
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220 | (1) |
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Clock Signals and Clocked Flip-Flops |
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221 | (3) |
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224 | (3) |
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227 | (3) |
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230 | (2) |
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D Latch (Transparent Latch) |
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232 | (1) |
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233 | (3) |
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236 | (2) |
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Flip-Flop Timing Considerations |
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238 | (3) |
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Potential Timing Problem in FF Circuits |
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241 | (2) |
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243 | (1) |
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Flip-Flop Synchronization |
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243 | (1) |
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Detecting an Input Sequence |
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244 | (1) |
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Data Storage and Transfer |
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245 | (2) |
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Serial Data Transfer: Shift Registers |
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247 | (3) |
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Frequency Division and Counting |
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250 | (4) |
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Microcomputer Application |
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254 | (2) |
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256 | (1) |
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One-Shot (Monostable Multivibrator) |
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256 | (4) |
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260 | (4) |
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Troubleshooting Flip-Flop Circuits |
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264 | (4) |
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Sequential Circuits Using HDL |
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268 | (4) |
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272 | (5) |
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HDL Circuits with Multiple Components |
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277 | (19) |
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Digital Arithmetic: Operations and Circuits |
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296 | (64) |
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298 | (1) |
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Representing Signed Numbers |
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299 | (7) |
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Addition in the 2's-Complement System |
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306 | (1) |
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Subtraction in the 2's-Complement System |
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307 | (3) |
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Multiplication of Binary Numbers |
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310 | (1) |
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311 | (1) |
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312 | (2) |
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314 | (3) |
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317 | (1) |
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318 | (2) |
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320 | (3) |
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Complete Parallel Adder with Registers |
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323 | (2) |
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325 | (1) |
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Integrated-Circuit Parallel Adder |
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326 | (2) |
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328 | (3) |
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331 | (4) |
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Troubleshooting Case Study |
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335 | (2) |
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Using TTL Library Functions with HDL |
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337 | (1) |
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Logical Operations on Bit Arrays |
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338 | (2) |
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340 | (3) |
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Expanding the, Bit Capacity of a Circuit |
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343 | (17) |
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360 | (128) |
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Asynchronous (Ripple) Counters |
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362 | (3) |
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Propagation Delay in Ripple Counters |
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365 | (2) |
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Synchronous (Parallel) Counters |
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367 | (3) |
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Counters with MOD Numbers <2N |
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370 | (7) |
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Synchronous Down and Up/Down Counters |
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377 | (2) |
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379 | (1) |
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380 | (9) |
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389 | (4) |
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Analyzing Synchronous Counters |
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393 | (3) |
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Synchronous Counter Design |
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396 | (9) |
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Basic Counters Using HDLs |
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405 | (7) |
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Full-Featured Counters in HDL |
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412 | (5) |
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Wiring HDL Modules Together |
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417 | (8) |
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425 | (12) |
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Integrated-Circuit Registers |
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437 | (1) |
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Parallel In/Parallel Out---The 74ALS174/74HC174 |
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437 | (2) |
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Serial In/Serial Out---The 74ALS166/74HC166 |
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439 | (2) |
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Parallel In/Serial Out---The 74ALS165/74HC165 |
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441 | (2) |
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Serial In/Parallel Out---The 74ALS164/74HC164 |
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443 | (2) |
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445 | (5) |
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450 | (2) |
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452 | (7) |
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459 | (2) |
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461 | (27) |
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Integrated-Circuit Logic Families |
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488 | (88) |
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490 | (8) |
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498 | (4) |
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502 | (4) |
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TTL Series Characteristics |
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506 | (3) |
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509 | (5) |
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Other TTL Characteristics |
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514 | (4) |
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518 | (3) |
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521 | (2) |
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CMOS Series Characteristics |
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523 | (7) |
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530 | (3) |
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Open-Collector/Open-Drain Outputs |
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533 | (5) |
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Tristate (Three-State) Logic Outputs |
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538 | (3) |
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High-Speed Bus Interface Logic |
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541 | (2) |
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The ECL Digital IC Family |
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543 | (3) |
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CMOS Transmission Gate (Bilateral Switch) |
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546 | (2) |
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548 | (5) |
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Mixed-Voltage Interfacing |
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553 | (1) |
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Analog Voltage Comparators |
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554 | (2) |
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556 | (20) |
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576 | (100) |
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577 | (7) |
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BCD-to-7-Segment Decoder/Drivers |
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584 | (3) |
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587 | (4) |
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591 | (6) |
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597 | (2) |
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Multiplexers (Data Selectors) |
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599 | (5) |
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604 | (6) |
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Demultiplexers (Data Distributors) |
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610 | (7) |
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617 | (4) |
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621 | (3) |
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624 | (4) |
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628 | (1) |
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The 74ALS173/HC173 Tristate Register |
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629 | (3) |
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632 | (6) |
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638 | (4) |
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The HDL 7-Segment Decoder/Driver |
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642 | (3) |
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645 | (3) |
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HDL Multiplexers and Demultiplexers |
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648 | (4) |
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HDL Magnitude Comparators |
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652 | (1) |
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653 | (23) |
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Digital System Projects Using HDL |
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676 | (42) |
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678 | (1) |
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Stepper Motor Driver Project |
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679 | (8) |
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687 | (6) |
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693 | (17) |
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Frequency Counter Project |
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710 | (8) |
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Interfacing with the Analog World |
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718 | (66) |
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Review of Digital Versus Analog |
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719 | (2) |
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Digital-to-Analog Conversion |
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721 | (7) |
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728 | (5) |
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733 | (2) |
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An Integrated-Circuit DAC |
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735 | (1) |
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736 | (2) |
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738 | (1) |
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Analog-to-Digital Conversion |
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739 | (1) |
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740 | (5) |
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745 | (4) |
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Successive-Approximation ADC |
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749 | (6) |
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755 | (2) |
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Other A/D Conversion Methods |
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757 | (4) |
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761 | (1) |
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762 | (2) |
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Digital Storage Oscilloscope |
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764 | (1) |
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Digital Signal Processing (DSP) |
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765 | (19) |
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784 | (84) |
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786 | (4) |
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790 | (3) |
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793 | (2) |
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795 | (1) |
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796 | (3) |
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799 | (1) |
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800 | (8) |
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808 | (3) |
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811 | (3) |
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814 | (1) |
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815 | (3) |
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818 | (5) |
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823 | (1) |
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Dynamic RAM Structure and Operation |
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824 | (5) |
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829 | (2) |
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831 | (3) |
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834 | (2) |
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Expanding Word Size and Capacity |
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836 | (8) |
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844 | (3) |
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Troubleshooting RAM Systems |
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847 | (5) |
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852 | (16) |
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Programmable Logic Device Architectures |
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868 | (30) |
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Digital Systems Family Tree |
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870 | (5) |
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Fundamentals of PLD Circuitry |
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875 | (2) |
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877 | (4) |
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The GAL 16V8 (Generic Array Logic) |
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881 | (4) |
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885 | (5) |
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The Altera FLEX10K Family |
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890 | (4) |
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The Altera Cyclone Family |
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894 | (4) |
Glossary |
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898 | (13) |
Answers to Selected Problems |
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911 | (8) |
Index of ICs |
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919 | (3) |
Index |
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922 | |