On-Chip Esd Protection for Integrated Circuits

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Format: Hardcover
Pub. Date: 2002-01-01
Publisher(s): Kluwer Academic Pub
List Price: $262.49

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Summary

This comprehensive and insightful book discusses ESD protection circuit design problems from an IC designer's perspective. On-Chip ESD Protection for Integrated Circuits: An IC Design Perspective provides both fundamental and advanced materials needed by a circuit designer for designing ESD protection circuits, including: Testing models and standards adopted by U.S. Department of Defense, EIA/JEDEC, ESD Association, Automotive Electronics Council, International Electrotechnical Commission, etc. ESD failure analysis, protection devices, and protection of sub-circuits Whole-chip ESD protection and ESD-to-circuit interactions Advanced low-parasitic compact ESD protection structures for RF and mixed-signal IC's Mixed-mode ESD simulation-design methodologies for design prediction ESD-to-circuit interactions, and more! Many real world ESD protection circuit design examples are provided. The book can be used as a reference book for working IC designers and as a textbook for students in the IC design field.

Author Biography

Albert Z.H. Wang received his PhD in Electrical Engineering from The State University of New York at Buffalo in 1995. After working for National Semiconductor Corporation in Santa Clara, CA, as a Staff R&D Engineer, he joined the Electrical and Computer Engineering Department at Illinois Institute of Technology in 1998. His research interests and publications center on analog, mixed-signal, RF and SoC IC design, on-chip ESD protection circuit design, IC CAD, and other closely related subjects.

Table of Contents

Dedication v
Table of Contents
vii
Acknowledgements xiii
Preface xv
Introduction
1(10)
A Little Historical Story
1(1)
ESD Failure - an IC Reliability Problem
2(2)
On-Chip ESD Protection - General Remedy
4(2)
Challenges in ESD Protection Design
6(1)
Scope of This Book
7(4)
References
9(2)
ESD Test Models
11(24)
Nature of ESD Phemonema
11(3)
HBM Model
14(4)
MM Model
18(3)
CDM Model
21(3)
TLP Model
24(3)
Other Models
27(3)
ESD Zapping Tests
30(1)
Summary
31(4)
References
33(2)
ESD Protection Device Solutions
35(38)
On-Chip ESD Protection Mechanisms
35(2)
Diode as ESD Protection Element
37(5)
Diode Device Physics
37(3)
Diode in ESD Protection Operation
40(1)
Diode Parasitic Modelling
41(1)
BJT as ESD Protection Element
42(9)
BJT Device Physics
42(4)
BJT in ESD Protection Operation
46(3)
BJT Parasitic Modelling
49(2)
MOSFET as ESD Protection Element
51(8)
MOSFET Device Physics
51(3)
ggMOSFET in ESD Protection Operation
54(3)
MOSFET Parasitic Modelling
57(2)
SCR as ESD Protection Element
59(11)
SCR Device Physics
59(5)
SCR in ESD Protection Operation
64(3)
SCR Parasitic Modelling
67(3)
Summary
70(3)
References
71(2)
ESD Protection Circuit Solutions
73(34)
Input ESD Protection Schemes
73(16)
A Primary-Secondary ESD Protection Network
74(1)
Multiple-Finger ESD Protection Structure
75(2)
Gate-Coupled MOS ESD Protection Structure
77(3)
BJT ESD Protection Network
80(5)
SCR ESD Protection Network
85(4)
Output ESD Protection Schemes
89(6)
Dedicated Output ESD Protection Network
90(5)
Self-Protection of Output Stages
95(1)
Power Clamps
95(9)
NMOS Power Clamp
96(1)
SCR Power Clamp
97(1)
Diode String Power Clamp
98(4)
Switch as Power Clamp
102(2)
Summary
104(3)
References
105(2)
Advanced ESD Protection
107(28)
Mixed-Signal
ESD Protection for Mixed-Signal ICs
107(1)
ESD Protection for RF ICs
108(5)
Low-Parasitic Multiple-Mode Solutions
113(13)
A Dual-Direction ESD Protection Structure
115(6)
An All-in-One Multiple-Mode ESD Protection Design
121(5)
Whole-Chip ESD Protection Schemes
126(4)
Principles for Full-Chip ESD Protection
127(1)
A Pad + Clamp Scheme
127(2)
A Common ESD Discharge Bus Scheme
129(1)
Non-Portability in ESD Protection
130(1)
Summary
131(4)
References
132(3)
ESD Failure Analysis and Modeling
135(36)
Why ESD Failure Analysis?
135(1)
ESD FA Techniques
136(2)
Some ESD Failure Signatures
138(17)
ESD FA Correlation
155(4)
Latent ESD Failure
159(3)
ESD Failure Modeling and Criteria
162(3)
Summary
165(6)
References
167(4)
Layout and Technology Influences on ESD Protection Circuit Design
171(48)
Layout vs. ESD Protection
171(1)
Regular Layout for ESD Protection
172(11)
Special Layout for ESD Protection
183(10)
Advanced Layout Design Concepts
193(12)
Technology Scaling vs. ESD Protection
205(1)
New Technology vs. ESD Protection
206(4)
ESD Protection for SOI and SiGe
210(5)
ESD Protection for Nano Technology
215(1)
Summary
216(3)
References
217(2)
ESD Simulation-Design Methodologies
219(42)
ESD Protection Design Methods: Trial-&-Error versus Predictive
219(2)
ESD Design-Simulation: Device Level versus Circuit Level
221(3)
ESD Protection Device Modeling
224(5)
Mixed-Mode ESD Simulation for Design Prediction
229(5)
Mixed-Mode ESD Simulation: Case Study
234(21)
Understanding ESD Simulation Results
235(4)
Case 1: NMOS ESD Protection Structures in 0.8μm BiCMOS
239(7)
Case 2: MOS ESD Protection Circuit in 0.35μm CMOS
246(3)
Case 3: Metal Interconnect in ESD Protection Design
249(2)
Case 4: A Dual-Direction ESD Protection Structure in BiCMOS
251(4)
ESD Protection Design Verification
255(1)
Summary
256(5)
References
258(3)
ESD - Circuit Interactions
261(22)
Chip-Level ESD Protection Design
261(1)
Circuit-to-ESD Influences: Pre-Mature ESD Failures
262(6)
ESD-to-Circuit Influences: Circuit Performance Degradation
268(12)
Summary
280(3)
References
282(1)
Conclusion Remarks and Future Work
283(4)
Conclusion Remarks
283(2)
Future Work
285(2)
Appendix A SUMMARY FOR ESD TEST STANDARDS 287(6)
References
291(2)
Appendix B COMMERCIAL ESD TESTING SYSTEMS 293(2)
Appendix C ESD PROTECTION CIRCUIT DESIGN CHECKLIST 295(4)
Index 299

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