Field-Programmable Logic and Applications,9783540664574

Field-Programmable Logic and Applications

by ; ; ;
ISBN13: 9783540664574
ISBN10: 3540664572
Format: Paperback
Pub. Date: 1999-11-01
Publisher(s): Springer Verlag
List Price: $136.49

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Summary

This volume constitutes the refereed proceedings of the 9th International Workshop on Field-Programmable Logic and Applications, FPL'99, held in Glasgow, Scotland, UK, in August 1999. The 33 revised full papers and the 32 posters presented in the volume were carefully reviewed and selected from a large number of submissions. The papers are organized in topical sections on signal processing, CAD tools for dynamically reconfigurable logic, optimization studies, physical design, dynamically reconfigurable logic, design tools, reconfigurable computing, applications, novel architectures, and machine applications.

Table of Contents

Signal Processing
Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing
1(10)
P. Graham
B. Nelson
Auditory Signal Processing in Hardware: A Linear Gammatone Filterbank Design for a Model of the Auditory System
11(10)
M. Brucke
A. Schulz
W. Nebel
SONIC - A Plug-In Architecture for Video Processing
21(10)
S. D. Haynes
P. Y. K. Cheung
W. Luk
J. Stone
CAD Tools for DRL
DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems
31(10)
K. Bondalapati
V. K. Prasanna
Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems Using the DCS CAD Framework
41(10)
D. Robinson
P. Lysaght
Optimization Studies
Optimal Finite Field Multipliers for FPGAs
51(10)
G. C. Ahlquist
B. Nelson
M. Rice
Memory Access Optimization and RAM Inference for Pipeline Vectorization
61(10)
M. Weinhardt
W. Luk
Analysis and Optimization of 3-D FPGA Design Parameters
71(10)
S. M. S. A. Chiricescu
M. M. Vai
Physical Design
Tabu Search: Ultra-Fast Placement for FPGAs
81(10)
J. M. Emmert
D. K. Bhatia
Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies
91(10)
J. de Vicente
J. Lanchares
R. Hermida
Hierarchical Interactive Approach to Partition Large Designs into FPGAs
101(10)
H. Krupnova
G. Saucier
Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays
111(13)
W. K. C. Ho
S. J. E. Wilton
Dynamically Reconfigurable Logic
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically. Reconfigurable Logic Systems
124(10)
M. Vasilko
A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic
134(10)
E. Canto
J. M. Moreno
J. Cabestany
J. Faura
J. M. Insenser
Self Controlling Dynamic Reconfiguration: A Case Study
144(11)
G. McGregor
P. Lysaght
Design Tools
An Internet Based Development Framework for Reconfigurable Computing
155(10)
R. W. Hartenstein
M. Herz
U. Nageldinger
T. Hoffmann
On Tool Integration in High-Performance FPGA Design Flows
165(10)
A. Koch
Hardware-Software Codesign for Dynamically Reconfigurable Architectures
175(10)
K. S. Chatha
R. Vemuri
Reconfigurable Computing
Serial Hardware Libraries for Reconfigurable Designs
185(10)
W. Luk
A. Derbyshire
S. Guo
D. Siganos
Reconfigurable Computing in Remote and Harsh Environments
195(10)
G. Brebner
N. Bergmann
Communication Synthesis for Reconfigurable Embedded Systems
205(10)
M. Eisenring
M. Platzner
L. Thiele
Run-Time Parameterizable Cores
215(8)
S. A. Guccione
D. Levi
Applications
Rendering PostScript™ Fonts on FPGAs
223(10)
D. MacVicar
J. W. Patterson
S. Singh
Implementing Photoshop™ Filters in Virtex™
233(10)
S. Ludwig
R. Slous
S. Singh
Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler
243(10)
K. Feske
M. Scholz
G. Doring
D. Nareike
Quantitative Analysis of Run-Time Reconfigurable Database Search
253(11)
N. Shirazi
W. Luk
D. Benyamin
P. Y. K. Cheung
Novel Architectures
An On-Line Arithmetic Based FPGA for Low-Power Custom Computing
264(10)
A. Tisserand
P. Marchal
C. Piguet
A New Switch Block for Segmented FPGAs
274(8)
M. I. Masud
S. J. E. Wilton
PulseDSP - A Signal Processing Oriented Programmable Architecture
282(9)
G. Jones
Machine Applications
FPGA Viruses
291(10)
I. Hadzic
S. Udani
J. M. Smith
Genetic Programming Using Self Reconfigurable FPGAs
301(12)
R. P. S. Sidhu
A. Mei
V. K. Prasanna
Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs
313(10)
A. Oliveira
A. Melo
V. Sklyarov
Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs
323(10)
G. A. Constantinides
P. Y. K. Cheung
W. Luk
Short Papers
An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes
333(6)
H. Kropp
C. Reuter
M. Wiege
T.-T. Do
P. Pirsch
An FPGA Implementation of Goertzel Algorithm
339(8)
T. Dulik
Pipelined Multipliers and FPGA Architectures
347(6)
M. Wojko
FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding
353(6)
E. M. Popovici
P. Fitzpatrick
C. C. Murphy
Reconfigurable Multiplier for Virtex FPGA Family
359(6)
J. Poldre
K. Tammemae
Pipelined Floating Point Arithmetic Optimised for FPGA Architectures
365(6)
I. Stamoulis
M. White
P. F. Lister
SL - A Structural Hardware Design Language
371(6)
S. Holmstrom
High-Level Hierarchical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules
377(8)
R. B. Maunder
Z. A. Salcic
G. G. Coghill
Mapping Applications onto Reconfigurable KressArrays
385(6)
R. Hartenstein
M. Herz
T. Hoffmann
U. Nageldinger
Global Routing Models
391(5)
M. Danek
Z. Muzikar
Power Modelling in Field Programmable Gate Arrays (FPGA)
396(9)
A. Garcia
W. Burleson
J.-L. Danger
NEBULA: A Partially and Dynamically Reconfigurable Architecture
405(6)
D. Bhatia
K. S. Sinha
P. Kannan
High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects
411(6)
K. J. Symington
J. F. Snowdon
H. Schroeder
AHA-GRAPE: Adaptive Hydrodynamic Architecture GRAvity PipE
417(8)
T. Kuberka
A. Kugel
R. Manner
H. Singpiel
R. Spurzem
R. Klessen
DIME - The First Module Standard for FPGA Based High Performance Computing
425(6)
M. Devlin
A. J. Cantle
The Proteus Processor - A Conventional CPU with Reconfigurable Functionality
431(7)
M. Dales
Logic Circuit Speeding up through Multiplexing
438(6)
V. F. Tomashau
A Wildcarding Mechanism for Acceleration of Partial Configurations
444(6)
P. James-Roxby
E. Cerro-Prada
Hardware Implementation Techniques for Recursive Calls and Loops
450(6)
T. Maruyama
M. Takagi
T. Hoshino
A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation
456(6)
J. Noguera
R. M. Badia
J. Domingo
J. Sole-Pareta
An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis
462(7)
M. D. Valdes
M. J. Moure
E. Mandado
A. Salaverria
Reconfigurable Programming in the Large on Extendable Uniform Reconfigurable Computing Array's: An Integrated Approach Based on Reconfigurable Virtual Architectures
469(6)
A. Touhafi
W. Brissinck
E. F. Dirk
A Concept for an Evaluation Framework for Reconfigurable Systems
475(6)
S. Sawitzki
R. G. Spallek
Debugging Application-Specific Programmable Products
481(6)
R. Kress
A. Pyttel
IP Validation for FPGAs Using Hardware Object Technology™
487(8)
S. Casselman
J. Schewel
C. Beaumont
A Processor for Artificial Life Simulation
495(6)
M. Boge
A. Koch
A Distributed, Scalable, Multi-Layered Approach to Evolvable System Design Using FPGA's
501(6)
C. Slorach
S. Fulton
K. Sharman
Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching
507(7)
T. Caohuu
T. Trong Le
M. Glesner
J. Becker
A Reconfigurable Architecture for High Speed Computation by Pipeline Processing
514(6)
T. Maruyama
T. Hoshino
Seeking (the right) Problems for the Solutions of Reconfigurable Computing
520(6)
B. Kastrup
J. van Meerbergen
K. Nowak
A Runtime Reconfigurable Implementation of the GSAT algorithm
526(6)
H. Y. Wong
W. S. Ynen
K. H. Lee
P. H. W. Leong
Accelerating Boolean Implications with FPGAs
532(7)
K. Sulimma
D. Stoffel
W. Kunz
Author Index 539

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