Computer Architecture and Implementation

by
Format: Hardcover
Pub. Date: 2000-02-13
Publisher(s): Cambridge University Press
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Summary

This textbook provides a clear and concise introduction to computer architecture and implementation. Two important themes are interwoven throughout the book. The first is an overview of the major concepts and design philosophies of computer architecture and organization. The second is the early introduction and use of analytic modeling of computer performance. The author begins by describing the classic von Neumann architecture, and then presents in detail a number of performance models and evaluation techniques. He goes on to cover user instruction set design, including RISC architecture. A unique feature of the book is its memory-centric approach - memory systems are discussed before processor implementations. The author also deals with pipelined processors, input/output techniques, queuing modes, and extended instruction set architectures. Each topic is illustrated with reference to actual IBM and Intel architectures. The book contains many worked examples and over 130 homework exercises. It is an ideal textbook for a one-semester undergraduate course in computer architecture and implementation.

Table of Contents

Preface viii
Computer Overview
1(25)
Introduction
1(1)
von Neumann Model
2(3)
The von Neumann Architecture
5(8)
The von Neumann Instruction Set Architecture
6(4)
Instruction Interpretation Cycle
10(3)
Limitations of the von Neumann Instruction Set Architecture
13(1)
Historical Notes
13(13)
Precursors to the von Neumann Instruction Set Architecture
14(9)
References
23(1)
Exercises
24(2)
Performance Models and Evaluation
26(24)
Introduction
26(1)
Performance Models
26(11)
Amdahl's Law
37(2)
Moore's Law
39(3)
Learning Curve
42(2)
Grosch's Law
44(1)
Steady-State Performance
45(1)
Transient Performance
46(4)
References
47(1)
Exercises
47(3)
User Instruction Set Design
50(81)
Introduction
50(1)
Lexical Level
51(1)
Instruction Set Architecture
51(47)
Addresses
53(9)
Operations
62(12)
Data Types
74(1)
User Data Types
75(13)
Program Sequencing Data Types
88(5)
Instruction Composition
93(5)
CISC and RISC Architectural Styles
98(5)
Static and Dynamic Instruction Statistics
103(6)
Arithmetic
109(22)
Addition/Subtraction
111(3)
Multiplication and Division
114(4)
Floating-Point Arithmetic
118(3)
Precision Treatment
121(6)
References
127(1)
Exercises
128(3)
Memory Systems
131(52)
Introduction
131(1)
Hierarchical Memory
132(1)
Paged Virtual Memory
133(12)
Caches
145(18)
Interleaved Real Memory
163(8)
Virtual-and Real-Address Caches
171(2)
Segmented Virtual Memory
173(3)
Disk Memory
176(3)
System Operation
179(4)
References
181(1)
Exercises
181(2)
Processor Control Design
183(21)
Introduction
183(2)
Hardwired Control
185(8)
Microprogrammed Control
193(11)
References
201(1)
Exercises
202(2)
Pipelined Processors
204(37)
Introduction
204(1)
Performance Models
205(2)
Pipeline Partitioning
207(4)
Pipeline Delays
211(20)
Branch Delays
212(13)
Structural Hazards
225(2)
Data Dependencies
227(4)
Interrupts
231(3)
Superscalar Pipelines
234(3)
Pipelined Processor Memory Demand
237(4)
References
239(1)
Exercises
239(2)
Input/Output
241(34)
Introduction
241(1)
I/O System Architecture
241(8)
I/O Device Requirements
249(3)
Buses and Controllers
252(6)
Bus Design Examples
258(1)
Serial Communication
258(5)
Clock Synchronization
263(2)
Queuing Theory
265(10)
Open-System Queuing Model
265(6)
Closed-System Queuing Model
271(2)
References
273(1)
Exercises
274(1)
Extended Instruction Set Architectures
275(35)
Introduction
275(1)
Operating System Kernel Support
276(7)
Virtual-Memory Support
283(7)
Interrupt Support
290(3)
Input/Output Support
293(2)
Cache Support
295(3)
Multiprocessor Support
298(4)
Other User ISA Enhancements, MMX
302(8)
Other Intel ISA Support
307(1)
References
308(1)
Exercises
308(2)
Index 310(8)
Trademarks 318

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